In the manufacturing of the semiconductor devices, a widely utilized and cost efficient type of manufacturing process offered by many foundries is the standard process (or bulk cmos processing). In standard process manufacturing of semiconductor devices, referring to FIG. 1a, as an illustration, a bulk substrate doped to be p- 100 and one or more n- wells 101 may be deposited thereon. Within the well 101, one method of electrically isolating the active device regions is to form a trench isolation region 104 between adjacent devices 106. Such prior art trench isolation regions typically comprise a trench that is formed within the substrate and filled with a dielectric material such as SiO2. Active device regions can also be formed outside of the well separated by one or more isolation regions. The active devices can be any semiconductor devices. Here, CMOS devices are illustrated 106 each having drain, source, and gate terminals 102, 103, and 110. Each of the active devices can be a pmos or an nmos.
Three categories of trench isolation regions are known, including shallow trenches (trenches whose depth is less than about 1 um), moderate trenches (trenches whose depth is from about 1 to about 3 mum), and deep trenches (trenches whose depth is greater than 3 mum). Note that the exact depth can be relative and not necessarily be the measurements provided here. As the size of the semiconductor devices is continuously being scaled down, there is a greater interest in employing shallow trench isolation (“STI”) regions. The active device regions 106 may have an insulation layer 108 and a poly layer 110 acting as the gate for the device.
FIG. 1b illustrates yet another prior art silicon-on-insulate (“SOI”) process where an insulation layer 122 is deposited on a wafer substrate 120, and the insulation layer can be a dielectric material such as SiO2 having a high k constant. On top of the insulation layer 122, there are active devices 124, 126, and 128, that may be separated by regions 132, 134, 135, and 138 that are doped accordingly. Each active device has a couple of terminals 130, 134, and a channel 132. Note that the active devices may have different types of doping. Here, devices 124 and 128 have n- channels and p+ terminals, while device 126 has a p- channel and n+ terminals.
While the standard process presents offers cost advantages in the manufacturing of semiconductor devices, but using the standard process in the manufacturing of a memory cell still requires the use of a 6-transister structure (and in some cases a 4-transistor structure) for a memory cell. Thus, for certain applications, the space required on a die for the memory block can be quite significant. For example, many system-on-a-chip applications require large blocks of memory cells, requiring large real estate on the die and an expensive application.
As the geometry of the semiconductor devices continue to shrink, there is a strong desire to shrink the memory cell/memory block as well. However, given the 6-transister (and 4-transister) memory cell structure, it is difficult to shrink the memory cell using the standard process of manufacturing.
Furthermore, generally speaking, memory devices require different, and quite often proprietary, type of manufacturing processes. Thus, memory devices are more expensive to manufacture and any proprietary processes might require an entirely new foundry all together, raising the entry barrier even higher.
Accordingly, there is a desire for manufacturing memory devices utilizing cost-efficient standard process of manufacturing.